Latch-up is a failure of CMOS, BiCMOS and bipolar integrated circuits (ICs) characterized by excessive current drain coupled with functional failure, parametric failure and/or device destruction. Circuits are manually made in silicon by combining adjacent p-type and n-type regions (i.e. over-seeded or “doped” with appropriate impurities) into transistors. Paths other than those chosen to form the desired transistor can sometimes result in so-called parasitic transistors which, under normal conditions, cannot be activated. Latch-up occurs as a result of interaction between the parasitic bipolar transistors always present in CMOS, bipolar and BiCMOS devices, caused by a spurious current spike, such that a pair of such parasitic transistors combine into a circuit with large positive feedback.
Referring to FIG. 1 of the drawings, there is illustrated schematically a CMOS inverter, and the desired circuit thereof is illustrated schematically in FIG. 2 of the drawings. The parasitic PNP and NPN transistors form a parasitic PNPN device, in which the collector of the parasitic PNP transistor feeds the base of the parasitic NPN transistor, and the collector of the parasitic NPN transistor feeds the base of the parasitic PNP transistor, as illustrated in the circuit diagram of FIG. 3. When latch-up occurs, a positive feedback takes place, causing a large current flow between the supply voltage line (VDD) and the ground line (VSS) of the integrated circuit, causing the circuit of FIG. 3 to turn fully on and cause a short circuit across the device, thereby preventing correct operation of the IC and causing discharge of the supply source or burn-up of the IC. Similar combinations of parasitic bipolar devices occur also in BiCMOS and bipolar technologies.
The I-V characteristic of the PNPN configuration illustrated in FIG. 3 is shown in FIG. 4 of the drawings. When a current larger than the trigger current, or a voltage larger than the trigger voltage, is fed to the structure, a snap-back phenomenon occurs in the PNPN parasitic device and the current suddenly increases. When the trigger is removed, the high current continues to flow if the holding voltage is lower than the IC supply voltage. If the holding voltage is larger than the IC supply voltage, the IC is said to be ‘latch-up free’, because once the above-mentioned trigger is removed, the IC continues to function correctly. The trigger stimulus can originate from several different sources, including, an ESD (electrostatic discharge) pulse during IC operation, a large current or voltage generated by device switching during IC operation, etc. In addition, the trigger current may be generated within the latching structure (of FIG. 3) or it may be generated elsewhere in the circuit and propagate to the latching structure.
During IC development, it is highly desirable to ensure that an integrated circuit is latch-up free, or at least that the maximum current that can reach the parasitic PNPN devices in the integrated circuit is less than the trigger current, in which case, the IC is said to be ‘latch-up immune’, because latch-up cannot be triggered. Most modem technologies, do not tend to be latch-up free, and as such have to be made latch-up immune.
Typically, integrated circuits are tested for their susceptibility to latch-up in two ways:                By applying a voltage and/or current stress to the IC input-output pins and then verifying whether such applied stress induces latch-up in the integrated circuit;        By measuring the latch up parameters (holding voltage, and trigger current and voltage) on special PNPN test modules, in respect of which all diffusions are externally contacted. An example of such a test module is illustrated schematically in FIG. 5 of the drawings, and comprises an IC substrate 1, a P-type well 2 (P-Well), an N-type well 3 (N-Well), a shallow trench isolation (STI) region (or LOCOS) 4, P-Well and N-Well contact diffusions 5 and 6 respectively, an N+ diffusion 7 in P-Well (N+ hot-active), a P+ diffusion 8 in N-Well (P+ hot-active), an inter-level dielectric (ILD) 9 and metal contacts 10 to the PNPN diffusions.        
The first method referred to above allows checking as to whether latch-up can be induced in the integrated circuit, having regard to the fact that within given specifications for the maximum stress values, the IC should be latch-up immune. Typically, a current or voltage stress is applied to the IC pins and it is determined whether or not latch-up occurs. This method provides an accurate method of checking the susceptibility of the IC to the occurrence of latch-up, i.e. the risk of the occurrence of latch-up in the IC during operation thereof. However, this test can only be applied very late in the IC market introduction flow, at a time when the IC has already been manufactured. In the case that latch-up occurs (i.e. the IC is determined not to be latch-up immune), it is not possible to discriminate if latch-up has occurred in the input-output circuitry or in the IC circuitry providing the chip required functions (i.e. the IC core), unless failure analysis techniques are employed. In the event that the design or manufacturing process is required to be improved to make the IC latch-up immune, then at this stage in the market introduction flow, the result is a significant additional cost in product development and a delay in the market introduction, which is obviously undesirable and may result in the IC being obsolete by the time it does reach the market. Furthermore, it is not possible using this method to study how latch-up depends on the design of the IC and on the manufacturing process (i.e. junction implants, STI shaping, etc).
The second method referred to above allows the study of the dependency of the latch-up parameters on the manufacturing process and design variables. It is possible to investigate how the latch-up parameters depend on the design by manufacturing different test modules in which the design parameters (such as the distance between hot-actives and well contacts, the distance between hot-actives, etc.) are varied. The dependency of the latch-up parameters on the manufacturing process can be investigated by running split diffusion lots in which some process parameters are varied. Since the PNPN test structures are standard test modules that can be manufactured independently of the IC design, this latch-up study can be performed early in the manufacturing process flow development, well before an IC is taped out and manufactured. Furthermore, the acquired knowledge can be applied to all subsequent IC designs. However, the typical PNPN test structures do not permit study of the effect of a current or voltage stress applied to the IC pins, since the stress testing is carried out directly on the PNPN by applying a stress current or voltage to the N+ hot-active 8 and to the P+ hot-active 9. As only a fraction of the current injected into the IC pins reaches the IC core, using the typical latch-up PNPN test modules leads to over-estimates of the maximum current which will actually reach the IC core. As a consequence, in order to make the IC latch-up immune, unnecessary design rules may be applied, with a resultant negative effect on IC performance and an undesirable increase in chip area.